1. Field of the Invention
The present invention relates generally to semiconductor memory devices for a simple cache system, and more particularly, to semiconductor memory devices having a cache memory integrated on a chip on which the semiconductor memory device is formed.
2. Description of the Prior Art
Conventionally, in order to improve cost performance of a computer system, a small capacity and high-speed memory has been frequently provided as a high-speed buffer between a main memory structured by a low-speed but large capacity and low-cost dynamic random access memory (DRAM) and a central processing unit (CPU). The high-speed buffer is referred to as a cache memory. A block of data which the CPU may request is copied from the main memory and stored in the high-speed buffer. The state in which data stored in an address, in the DRAM, which the CPU attempts to access exist in the cache memory is referred to as xe2x80x9chitxe2x80x9d. In this case, the CPU makes access to the high-speed cache memory, and acquires the requested data from the cache memory. On the other hand, the state in which data stored in an address which the CPU attempts to access does not exist in the cache memory is referred to as xe2x80x9ccache missxe2x80x9d. In this case, the CPU makes access to the low-speed main memory, acquires the requested data from the main memory and at the same time, transfers to the cache memory a data block to which the data belongs.
However, such a cache memory system could not be employed in a small-sized computer system attaching importance to the cost because it requires a high-cost and a high-speed memory. Conventionally, a simple cache system has been configured utilizing a high-speed access function of a general-purpose DRAM, such as a page mode and a static column mode.
FIG. 1 is a block diagram showing a basic structure of a conventional DRAM device having a function of a page mode or a static column mode.
In FIG. 1, a memory cell array 1 has a plurality of word lines and a plurality of bit line pairs arranged intersecting with each other, memory cells being provided at intersections thereof, respectively. In FIG. 1, there are typically shown only a single word line WL, a single bit line pair BL and {overscore (BL)} and a single memory cell MC provided at an intersection of the word line WL and the bit line BL. The word lines in the memory cell array 1 are connected to a row decoder portion 3 through a word driver 2. In addition, the bit line pairs in the memory cell array 1 are connected to a column decoder portion 6 through a sense amplifier portion 4 and an I/O switching portion 5. A row address buffer 7 is connected to the row decoder portion 3, and a column address buffer 8 is connected to the column decoder portion 6. A multiplex address signal MPXA obtained by multiplexing a row address signal RA and a column address signal CA is applied to the row address buffer 7 and the column address buffer 8. An output buffer 9 and an input buffer 10 are connected to the I/O switching portion 5.
FIGS. 2A, 2B and 2C are waveform diagrams showing operations in an ordinary read cycle, a page mode cycle and a static column mode cycle of the DRAM, respectively.
In the ordinary read cycle shown in FIG. 2A, the row address buffer 7 first acquires the multiplex address signal MPXA at the falling edge of a row address strobe signal {overscore (RAS)} and applies the same to the row decoder portion 3 as a row address signal RA. The row decoder portion 3 is responsive to the row address signal RA for selecting one of the plurality of word lines. The selected word line is activated by the word driver 2. Consequently, information stored in the plurality of memory cells connected to the selected word lines are read out onto the corresponding bit lines, respectively. The information are detected and amplified by the sense amplifier portion 4. At this time point, information stored in the memory cells corresponding to one row are latched in the sense amplifier portion 4. Then, the column address buffer 8 acquires the multiplex address signal MPXA at the falling edge of a column address strobe signal {overscore (CAS)} and applies the same to the column decoder portion 6 as a column address signal CA. The column decoder portion 6 is responsive to the column address signal CA for selecting one of information corresponding to one row latched in the sense amplifier portion 4. This selected information is extracted to the exterior through the I/O switching portion 5 and the output buffer 9 as output data DOUT. An access time ({overscore (RAS)} access time) tRAC in this case is the time period elapsed from the falling edge of the row address strobe signal {overscore (RAS)} until the output data DOUT becomes valid. In addition, a cycle time tc in this case is the sum of the time period during which the device is in an active state and an {overscore (RAS)} precharge time tRP. As a standard value, tc is approximately 200 ns when tRAC is 100 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 2B and 2C, memory cells on the same row address are accessed by changing the column address signal CA. In the page mode cycle, the column address signal CA is latched at the falling edge of the column address strobe signal {overscore (CAS)}. Thus, the access time is a time period tCAC (CAS access time) elapsed from the falling edge of the column address strobe signal {overscore (CAS)} until the output data DOUT becomes valid, which becomes a time period of approximately one-half of the access time tRAC in the ordinary cycle, i.e., approximately 50 ns, where tCP denotes a precharge time of the column address strobe signal {overscore (CAS)}, and tPC denotes a cycle time.
In the static column mode, access is made in response to only the change in the column address signal CA, as in a static RAM (SRAM). Thus, the access time is a time period tAA (address access time) from the time when the column address signal CA is changed to the time when the output data DOUT becomes valid, which becomes approximately one-half of the access time tRAC in the ordinary cycle similarly to tCAC, i.e., generally about 50 ns.
More specifically, in the page mode cycle, when the falling edge of the column address strobe signal {overscore (CAS)} is inputted to the column address buffer 8, the column address signal CA is sent to the column decoder. Therefore, any of the data corresponding to one row latched in the sense amplifier portion 4 is made valid, so that the output data DOUT is obtained through the output buffer 9. Also in the static column mode cycle, the same operation as that in the page mode cycle is performed except a reading operation is initiated in response to the change in address signal.
FIG. 3 is a block diagram showing a structure of a simple cache system utilizing the page mode or the static column mode of the DRAM device shown in FIG. 1. In addition, FIG. 4 is a waveform diagram showing an operation of the simple cache system shown in FIG. 3.
In FIG. 3, a main memory 20 comprises 1 M byte which comprises 8 DRAM devices 21 each having 1 Mxc3x971 organization. In this case, the row address signal RA and the column address signal CA having a total of 20 bits (220=1048576=1 M) are required. An address multiplexer 22, which applies 10-bit row address signal RA and the 10-bit column address signal CA to the main memory 20 two times, has 20 address lines A0 to A19 receiving a 20-bit address signal and 10 address lines A0 to A9 applying a 10-bit address signal as multiplexed (multiplex address signal MPXA) to the DRAM devices 21.
It is assumed here that data corresponding to one row selected by a row address RAL has been already latched in the sense amplifier portion 4 in each of the DRAM devices 21. An address generator 23 generates a 20-bit address signal corresponding to data which the CPU requests. The latch (TAG) 25 holds the row address RAL corresponding to data selected in the preceding cycle. A comparator 26 compares the 10-bit row address RA out of the 20-bit address signal with the row address RAL held in the TAG 25. When both coincide with each other, which means that the same row as that accessed in the preceding cycle is accessed (xe2x80x9chitxe2x80x9d), the comparator 26 generates an xe2x80x9cHxe2x80x9d level cache hit signal CH. A state machine 27 is responsive to the cache hit signal CH for performing page mode control in which a column address strobe signal {overscore (CAS)} is toggled (raised and then, lowered) with a row address strobe signal {overscore (RAS)} being kept at a low level. In response thereto, the address multiplexer 22 applies the column address signal CA to the DRAM devices 21 (see FIG. 4). Thus, data corresponding to the column address signal CA is extracted from a group of data latched in the sense amplifier portion in each of the DRAM devices 21. In the case of such xe2x80x9chitxe2x80x9d, output data is obtained from the DRAM devices 21 at high speed in an access time tCAC.
On the other hand, when the row address signal RA generated from the address generator 23 and the row address RAL held in the TAG 25 do not coincide with each other, which means that a different row from the row accessed in the preceding cycle is accessed (xe2x80x9ccache missxe2x80x9d), the comparator 26 does not generate the xe2x80x9cHxe2x80x9d level cache hit signal CH. In this case, the state machine 27 performs ordinary {overscore (RAS)} and {overscore (CAS)} control in the ordinary read cycle, and the address multiplexer 22 sequentially applies the row address signal RA and the column address signal CA to the DRAM devices 21 (see FIG. 4). In the case of such xe2x80x9ccache missxe2x80x9d, the ordinary read cycle beginning with precharging of the row address strobe signal {overscore (RAS)} occurs, so that output data is obtained at low speed in the access time tRAC. Therefore, the state machine 27 generates a wait signal Wait, to bring a CPU 24 into a Wait state. In the case of xe2x80x9ccache missxe2x80x9d, a new row address signal RA is held in the TAG 25.
As described in the foregoing, in the simple cache system shown in FIG. 3, data corresponding to one row of the memory cell array in each of the DRAM devices (1024 bits in the case of a 1 M bit device) is latched in a sense amplifier portion as one block. Therefore, the block size is unnecessarily large and the blocks (entries) held in the TAG 25 are insufficient in number. For example, in the system shown in FIG. 3, the number of entries becomes 1. Thus, only when access is continuously made to the same row address, cache hit occurs. Consequently, for example, when a program routine bridged over continuous two row addresses is repeatedly implemented, cache miss necessarily occurs, so that a cache hit rate is low.
Meanwhile, as another conventional example, a simple cache system has been proposed, which is disclosed in U.S. Pat. No. 4,577,293. In this simple cache system, a register holding data corresponding to one row is provided outside a memory cell array. In the case of xe2x80x9chitxe2x80x9d, the data is directly extracted from this register, so that accessing is speeded up. However, in the simple cache system disclosed in the U.S. Patent, the external register holds data corresponding to one row in the memory cell array, so that the block size is unnecessarily large and the cache hit rate is low as in the conventional example shown in FIGS. 1 and 3.
One object of the present invention is to provide a semiconductor memory device which can configure a high-speed simple cache system having a high cache hit rate.
Another object of the present invention is to provide a semiconductor memory device which can configure a simple cache system having an increased number of entries.
Still another object of the present invention is to provide a semiconductor memory device containing a cache memory in which an access time at the time of cache hit can be shorten.
Still another object of the present invention is to provide a semiconductor memory device containing a cache memory in which the number of entries of data can be increased without unnecessarily increasing the data block size.
A further object of the present invention is to provide an operating method for a semiconductor memory device which can configure a high-speed simple cache system having a high cache hit rate.
A still further object of the present invention is to provide an operating method for a semiconductor memory device containing a cache memory in which an access time at the time of cache hit can be shortened.
The semiconductor memory device according to the present invention is a semiconductor memory device containing a cache memory employed in a simple cache system including a generator for generating a cache hit/miss indicating signal, which comprises a first memory cell array, a second memory cell array, first access means, second access means, and data transfer means.
The first memory cell array comprises a plurality of memory cells arranged in a plurality of rows and columns. The second memory cell array comprises a plurality of static type memory cells arranged in a plurality of rows and a plurality of columns corresponding to the plurality of columns in the first memory cell array. The first access means is responsive to a cache miss indicating signal for accessing data to a memory cell selected by a first row address signal externally applied and a column address signal externally applied in the first memory cell array. The second access means is responsive to a cache hit indicating signal for accessing data to a static type memory cell selected by a second row address signal externally applied and the column address signal externally applied in the second memory cell array. The data transfer means transfers data between a row selected by the first row address signal externally applied in the first memory cell array and a row selected by the second row address signal externally applied in the second memory cell array.
In the semiconductor memory device according to the present invention, since the second memory cell array comprises a plurality of static type memory cells in a plurality of rows, data blocks on different rows in the first memory cell array can be held in the second memory cell array. Thus, the semiconductor memory device can configure a simple cache system in which the number of entries is increased so that a cache hit rate is improved.
In accordance with another aspect of the present invention, a semiconductor memory device for a simple cache system having a cache memory integrated on a chip on which the semiconductor memory device is formed comprises a first memory cell array, a second memory cell array, first access means, second access means, block selecting means, region selecting means, data transfer means and data selecting means.
The first memory cell array comprises a plurality of memory cells arranged in a plurality of rows and columns. The first memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The second memory cell array comprises a plurality of static type memory cells arranged in a plurality of rows and columns. The second memory cell array is divided into a plurality of regions each comprising the same number of a plurality of rows as the plurality of columns included in each of the plurality of blocks in the first memory cell array. The first access means accesses data to a memory cell selected by a first row address signal externally applied and a column address signal externally applied in the first memory cell array. The second access means accesses data to a static type memory cell selected by a cache address signal externally applied in the plurality of regions in the second memory cell array.
The block selecting means is responsive to a block selecting signal externally applied for selecting any of the plurality of blocks in the first memory cell array. The region selecting means is responsive to a region selecting signal externally applied for selecting any of the plurality of regions in the second memory cell array. The data transfer means transfers data between the a block, in the first memory cell array, selected by the block selecting means and the region, in the second memory cell array, selected by the region selecting means. Data selecting means is responsive to the region selecting signal for selecting any of data to/from the plurality of static type memory cells accessed by the second access means in the plurality of regions.
In this semiconductor memory device containing a cache memory, data blocks on the plurality of rows in the first memory cell array can be held on the second memory cell array. In addition, a plurality of data blocks respectively on a plurality of different rows in the same block in the first memory cell array can be simultaneously held in different regions in the second memory cell array. Furthermore, the data blocks respectively on the plurality of different rows in the same block in the first memory cell array can be arranged on one row in the second memory cell array.
Thus, if the second memory cell array is utilized as a cache memory, the number of entries of data can be efficiently increased, so that the cache hit rate can be improved. Additionally, access can be made to the second memory cell array before determination of cache hit/cache miss. In this case, data are extracted from the plurality of regions in the second memory cell array. Thereafter, when it is determined that cache hit occurs, any of the data extracted from the plurality of regions is selected. When it is determined that cache miss occurs, the data extracted from the second memory cell array is ignored. Thus, an access time at the time of cache hit can be shortened. As a result, semiconductor memory device can configure a high-speed simple set associative cache system having a high cache hit rate.